library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity counter_tb is
end entity counter_tb;

architecture structural of counter_tb is

	component counter is
		port (	clk		: in	std_logic;

			reset		: in	std_logic;
			count_out	: out	std_logic_vector (19 downto 0)
		);
	end component counter;

	signal	clk			: std_logic;
	signal	reset			: std_logic;
	signal	count_out		: std_logic_vector (19 downto 0);
	signal count_num :  integer;

begin


lbl0:	counter	port map (	clk		=> clk,
					reset		=> reset,
					count_out	=> count_out
			);

	clk		<= 	'0' after 0 ns,
		   		'1' after 10 ns when clk /= '1' else
				'0' after 10 ns;
	reset <= '1' after 0 ns,
	      '0' after 30 ns,
	      '1' after 30 ms,
	      '0' after 31 ms;
	count_num <= to_integer(unsigned(count_out));

end architecture structural;
